LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 460

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Table 21-4. Download Header Pinout
Note: Use of the DONE and INITN pins, while optional, does allow ispVM System to check that configuration com-
pleted successfully. If DONE or INITN are wired to the connector then the proper dialog box(es) must be checked in
the Cable and I/O Port Setup section of ispVM System. See the Software section of this document for more details.
1. VCCJ – V
2. TDO – Test Data Out: Serial data read from the test device to the cable.
3. TDI – Test Data In: Serial data written from the cable to the device.
4. PROGRAMN: Initiates a configuration sequence when asserted low. Not used and should not be con-
5. TRST – Test Reset: Not used and should not be connected on the board.
6. TMS – Test Mode Select: Controls the IEEE 1149.1 state machine.
7. TCK – Test Clock: Clocks the IEEE 1149.1 state machine.
8. GND: Digital ground.
9. DONE – Optional, USB Only: Open drain, internal pull-up. A high indicates that the FPGA configuration
10. INITN – Optional, USB Only: Open drain, internal pull-up. A high indicates that the FPGA is ready to be
V
TDO
TDI
PROGRAMN
TRST
TMS
GND
TCK
DONE
INITN
CCJ
nected on the board.
sequence 9 was completed successfully.
configured. A low indicates the FPGA is not ready to be configured, or an error occurred during configura-
tion.
Pin Name
CC
JTAG: Powers the ispDOWNLOAD Cable.
1x10
10
1
2
3
4
5
6
8
9
7
1x8
1
2
3
4
5
6
7
8
2, 4, 8
2x5
10
6
7
5
9
3
1
21-4
SPI Serial Flash Programming Using ispJTAG
Direction
Output
Output
Output
Output
Output
Input
Input
Input
—
—
3.3V or 2.5V
Test Data Out
Test Data In
Forces FPGA config, N/C
Test Reset, N/C
Test Mode Select
Ground
Test Clock
FPGA configuration complete, optional
FPGA ready for configuration, optional
on LatticeECP/EC FPGAs
Description