LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 402

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
How to Floorplan a Design
Design Performance Enhancement Strategies
Floorplanning methodologies improve the performance of designs that do not necessarily consist of individually
optimized modules. The ability of specifying regions to group nodes together and provide relative placement
enhances the usability of the ispLEVER place-and-route software tools. The design strategies for performance
enhancement depend on the structure of a particular circuit. Strategies include:
Note that designers may need to change existing design hierarchy and structure to make the design more amiable
to floorplanning. This is especially applicable if modular hierarchy and structure was not considered at the begin-
ning of design conception.
With the floorplaning methodologies, the user can choose to optimize modules either individually or after they have
been integrated with the top-level design. The user can exercise varying amounts of control over the placement by
using different types of regions. By using bounding boxes and location anchors selectively, the ispLEVER software
can easily determine the best size and location for a region. Another approach is to optimize the top-level design
without first optimizing the individual modules. This approach allows the ispLEVER software to place nodes within
regions and move regions across the device. The user assigns modules to regions and then compiles the entire
design. With this approach the user can place elements from different modules in a region.
Design Floorplanning Methodologies
There are several methods available to aid in the floorplanning of a logical design in a Lattice Semiconductor
FPGA. This section illustrates these methods with examples of how to use the ispLEVER software tools to achieve
performance goals. The three main floorplanning tools available include:
When to use PGROUP vs. UGROUP
UGROUPing differs from PGROUPing as follows:
In other words, PGROUPing enforces strict hierarchical control while UGROUPing allows for a grouping of blocks
in different hierarchies or a grouping of blocks with no hierarchy at all.
• Defining regions based on design hierarchy if the hierarchy closely resembles the structure of the circuit.
• Defining regions based on the critical path, if the critical path is long and spans multiple modules. Keeping
• Defining regions based on connections by grouping nodes with high fan-outs and high fan-ins together to
• The PGROUP Physical Constraint can be used as an attribute in VHDL and Verilog HDL source code or
• The UGROUP Logical Constraint can be used as an attribute in VHDL and Verilog HDL source code to
• The Floorplanner Graphical User Interface (GUI) can be used to interactively specify placement parame-
• A PGROUP logical identifier, in EDIF, is prepended with text that describes the identifier’s hierarchy.
• A UGROUP logical identifier, in EDIF, is not changed by prepending the hierarchy on the block instance
These designs typically consist of tightly integrated modules, where the logic for each module is self-con-
tained and modules communicate through well-defined interfaces.
the nodes in the critical path or the modules containing the critical path together may lead to improved per-
formance.
reduce delays in connections and wiring congestion in the device.
as a physical Preference in the .prf design constraint file. This can be used directly by the ispLEVER Placer
software to bound and locate sections of a design for grouping in the FPGA array.
gather logical sections of a design for grouping in the FPGA array.
ters in either the logical or physical domain for some of a design’s modules (e.g. logic gates, registers, arith-
metic functions) from one graphical user interface.
identifier.
16-4
Lattice Semiconductor Design Floorplanning