LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 339

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
LatticeECP/EC sysCONFIG Usage Guide
Table 12-2. The Flow Through option will drive out a static low signal on the CSON pin. The Flow Through option
will also tri-state the device D[0:7] and BUSY pins when configuration is completed on the device in order to not
interfere with the next daisy chained device to be configured.
Once the Flow Through option starts, the device will remain in Flow Through until the Wake-up sequence com-
pletes. One option to get out of the Flow Through option is to toggle CSN and CS1N, which will act as a reset sig-
nal. Refer to the Master Parallel Mode section of this document for more details.
Master Clock
When the user has determined that a device will be a Master, the CCLK will become an output clock with the fre-
quency set by the user. Until early in the configuration, the device is configured with a default Master Clock Fre-
quency of 2.5MHz. One of the first configuration bits set will be the Master Clock. See the device-specific section of
the CFG[0:2] descriptions.
The user can select which Master Clock frequency to use by setting the MCCLK_FREQ preference in the Lattice
design software. The MCCLK_FREQ preference will set the frequency of the Master Clock if selected by the
CONFIG_MODE and the CFG[0:2] pins. Default is the lowest frequency supported by the device. The user can
select a different clock speed, which will take effect just after configuration starts or if the device is reconfigured
prior to power down. Configuration time is computed by dividing the maximum configuration bits to be loaded, as
given in Figure 12-7, by the Master Clock frequency. See the LatticeECP/EC FPGA Family Data Sheet for
MCLK_FREQ selections.
SPI Mode
Mode
CFG[2]
CFG[1]
CFG[0]
CONFIG_MODE Parameter
SPI Master
0
0
0
SPI
The LatticeECP/EC devices offer a direct connection for memories that support the SPI standard. By setting the
configuration pins CFG[0:2] = b’000, the LatticeECP/EC devices will configure using the SPI interface. The SPI
interface offers several combinations of memory to FPGA.
1. One FPGA, one SPI Flash
2. Multiple FPGA, one SPI Flash
3. One FPGA, two SPI Flash
4. Multiple FPGA, multiple SPI Flash is not allowed because the circuitry to support serialization of multiple SPI
Flash through DOUT is not available.
For a more detailed discussion the EC/ECP to SPI interface requirements please refer to TN1078.
One FPGA, One SPI Flash
The simple SPI application is one SPI Flash serial connected to the SPID0 of the LatticeECP/EC devices in SPI
mode, as shown in Figure 12-1.
12-6