LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 301
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 301 of 478
- Download datasheet (13Mb)
Lattice Semiconductor
From the loop:
Assume f
Equation (6) becomes:
From equation (1):
Clock Distribution in LatticeECP/EC and LatticeXP
The clock inputs are selected from external I/Os, the sysCLOCK PLLs or general routing. These clock inputs are
fed through the chip via a clock distribution system.
LatticeECP/EC and LatticeXP devices provide a quadrant-based primary and secondary clock structure.
Primary Clock Sources and Distribution
Each quadrant has four primary clock nets: CLK0, CLK1, CLK2 and CLK3. CLK2 and CLK3 provide dynamic clock
selection (DCS) capability. Figure 11-8 illustrates the block diagram of the primary clock distribution.
Figure 11-8. Primary Clocks and Center Switch Boxes
Note: Two PLLs are available in LatticeECP/EC/XP-6 or smaller devices.
PLL*
PLL
f
f
f
f
f
f
f
PCLKT7
INMAX
OUTKMIN
OUTKMAX
INMIN
INMAX
OUTMIN
OUTMAX
INMAX
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
= ((f
= f
= (f
= 420
= f
= f
PFDMAX
= f
= f
VCOMAX
VCOMIN
INMIN
INMAX
OUTMIN
OUTMAX
* (N/M), if below 25 * N round up to 25 * N
* M = 420 * M
* (N/M), if above 420 round down to 420
/ (V*N))*M, if below 25 * M round up to 25 * M
/ (V*N))*M, if above 420 round down to 420
/ K
/ K
General
Routing
General
Routing
QUADRANT TL
QUADRANT BL
CLK0
CLK0
16:1
16:1
PLL*: For LatticeECP/EC/XP-10 and larger devices
Primary Clocks in Center Switch Box
CLK1
CLK1
16:1
16:1
12:1 12:1 12:1 12:1
12:1 12:1 12:1 12:1
CLK2
CLK2
DCS
DCS
CLK3
CLK3
DCS
DCS
11-11
12:1 12:1 12:1 12:1
12:1 12:1 12:1 12:1
sysCLOCK PLL Design and Usage Guide
DCS
DCS
CLK3
CLK3
CLK2
CLK2
DCS
DCS
QUADRANT TR
QUADRANT BR
CLK1
CLK1
16:1
16:1
LatticeECP/EC and LatticeXP
(10)
(11)
(12)
(13)
(9)
CLK0
CLK0
16:1
16:1
General
Routing
General
Routing
CLKOP
CLKOS
CLKOK
CLKOP
CLKOS
CLKOK
PCLKT2
PLL*
PLL
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