LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 350

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
DONE External
The LatticeECP/EC device can wake up on its own after the Done Bit is set or wait for the DONE pin to be driven
externally. The DONE_EX preference will determine if the wake-up sequence is triggered by an external DONE sig-
nal. The DONE_EX preference shall take a user entered ON or OFF. ON if the user wants to delay wake-up until
the DONE pin is driven high by an external signal and synchronous to the clock. The user will select OFF to syn-
chronously wake up when the internal Done bit is set and ignore any external driving of the DONE Pin. The default
for DONE_EX preference is OFF. If DONE_EX is set to ON, DONE_OD should be set to the default value of ON. If
and external signal is driving the DONE pin, it should be an open drain pin. See Table 12-6 for more information on
the relationship between DONE_OD and DONE_EX.
Table 12-6. Summary of DONE Pin Preferences (Preferences)
Master Clock Selection
When the user has determined that the LatticeECP/EC device will be a Master Configuration device and will pro-
vide the clocking source for configuration, the CCLK will become an output clock with the frequency set by the user.
At the start of configuration the device operates with the default Master Clock Frequency of 2.5MHz. One of the first
configuration bits set will be the Master Clock. Once the Master Clock configuration bits are set, the clock will start
operating at the user-defined frequency.
In order to control the Master Clock frequency, the MCCLK_FREQ preference can be set. The MCCLK_FREQ pref-
erence shall set the frequency of the MASTER clock if selected by the CONFIG_MODE and the CFG[0:2] pins.
See the LatticeECP/EC data sheet for the Master Clock frequencies supported by the MCLK_FREQ preference.
Security
When CONFIG_SECURE is set to ON, NO read back operation will be supported through the sysCONFIG port or
ispJTAG port of the configuration SRAM. The USERCODE register is readable and not considered securable.
Default is OFF. OFF indicates read back of the configuration memory is enabled through all ports.
Wake-up Sequence
The wake-up sequence controls three internal signals and the DONE pin will be driven post configuration and prior
to user mode. See the Wake-up Sequence section of this document for an example of the phase controls and the
device-specific section for specific info on the wake-up selections. The default setting for the WAKE_UP preference
will be determined by the DONE_EX setting.
Wake-up with DONE_EX = Off (Default setting)
The WAKE_UP preference will support the user-selectable options (1-25) as shown in Table 12-3. If the user does
not select a wake-up sequence, the default will be wake-up sequence 21 for DONE_EX preference set to OFF
(Default).
Wake-up with DONE_EX = On
The WAKE_UP preference will take the user selectable options (1-7) as shown in Table 12-3. If the user does not
select a wake-up sequence, the default will be wake-up sequence 4 for the DONE_EX preference set to ON.
Start_Up Clock Selection
Once the FPGA is configured, it enters the start-up state, which is the transition between the configuration and
operational states. This sequence is synchronized to a clock source, which defaults to CCLK when sysCONFIG is
used, or TCK when JTAG is used.
DONE_EX
OFF
ON
External DONE ignored
External DONE Low delays
Wake-up Process
12-17
LatticeECP/EC sysCONFIG Usage Guide
User selected
Set to Default (ON)
DONE_OD