LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 227
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
First In First Out (FIFO, FIFO_DC) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as First In First Out Memories –
FIFO and FIFO_DC. FIFO has a common clock for both read and write ports and FIFO_DC (or Dual Clock FIFO)
has separate clocks for these ports. IPexpress allows users to generate the Verilog-HDL or VHDL along with an
EDIF netlist for the memory size as per design requirement.
IPexpress generates the FIFO and FIFO_DC memory module as shown in Figures 9-31 and 9-32.
Figure 9-31. FIFO Module Generated by IPexpress
Figure 9-32. FIFO_DC Module Generated by IPexpress
LatticeECP/EC and LatticeXP devices do not have a built in FIFO. These devices have an emulated FIFO and
FIFO_DC. These are emulated by creating a wrapper around the existing RAMs (like RAM_DP). This wrapper also
includes address pointer generation and FIFO flag generation logic which will be implemented external to the EBR
block. Therefore, in addition to the regular EBR usage, there is extra logic for the address pointer generation and
FIFO flag generation.
A clock is always required as only synchronous write is supported. The various ports and their definitions for the
FIFO and FIFO_DC are included in Table 11.
RdClock
WrClock
Reset
Clock
WrEn
RdEn
Data
Reset
WrEn
RdEn
Data
EBR based First-In First-Out
EBR based First-In First-Out
Memory
Memory
FIFO
FIFO
9-28
LatticeECP/EC and LatticeXP Devices
Q
Full
Almost Full
Empty
Almost Empty
Q
Full
Almost Full
Empty
Almost Empty
Memory Usage Guide
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