LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 369

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
-- This VHDL example will be mapped into single MULT9X9MAC with the output register enabled
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mult_acc is
port (
end;
architecture arch of mult_acc is
begin
end process;
end arch;
The above RTL will infer the following block diagram.
Figure 15-10. MULT9X9MAC Block Diagram
As you can see, this block diagram can be mapped directly into the sysDSP primitives If we were to add a test point
between the multiplier and the accumulator, or two output registers, the code could not be mapped into a
MULT9X9MAC of a sysDSP Block. So options you could include in the design would be input registers, pipeline
registers, etc. For more inferring design examples refer to EXAMPLES in your ispLEVER software.
clk
dataax : in std_logic_vector(7 downto 0);
dataay : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(16 downto 0));
signal multout : std_logic_vector(15 downto 0);
signal adder_out : std_logic_vector(16 downto 0);
signal dataout_reg : std_logic_vector(16 downto 0);
multout <= dataax * dataay; -- 9x9 Multiplier
adder_out <= multout + dataout_reg;
process (clk)
begin
if (clk'event and clk='1') then
end if;
dataout <= dataout_reg;
dataout_reg <= adder_out; -- Output Register of the Accumulator
: in std_logic;
Multiplier
Accumulator
15-8
LatticeECP-DSP sysDSP Usage Guide
Register
Output
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