LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 185
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Values: NA, 2, 4, 8, 12, 16, 20
LatticeECP/EC Default: 6
LatticeXP Default: 8
The programmable drive available on a pad will depend on the V
for different V
Table 8-7. Programmable Drive Strength Values at Various V
PULLMODE
The PULLMODE attribute is available for all the LVTLL and LVCMOS inputs and outputs. This attribute can be
enabled for each I/O independently.
Values: UP, DOWN, NONE, KEEPER
Default: UP
PCICLAMP
PCI33 inputs and outputs on the top and bottom of the device have an optional PCI clamp that is enabled via the
PCICLAMP attribute. The PCICLAMP is also available for all LVCMOS33 and LVTTL inputs and outputs.
Values: ON, OFF
Default: OFF
SLEWRATE
The SLEWRATE attribute is available for all LVTTL and LVCMOS output drivers. Each I/O pin has an individual
slew rate control. This allows the designer to specify the slew rate control on a pin-by-pin basis.
Values: FAST, SLOW
Default: FAST
FIXEDDELAY
The FIXEDDELAY attribute is available to each input pin. When enabled, this attribute is used to achieve zero hold
time for the input registers when using global clock.
Values: TRUE, FALSE
Default: FALSE
DIN/DOUT
This attribute can be used when I/O registers need to be assigned. Using DIN will assert an input register and
using the DOUT attribute will assert an output register in the design. By default the software will try to assign the
I/O registers if applicable. The user can turn this OFF by using the synthesis attribute or using the preference editor
of the software. These attributes can only be applied on registers.
CCIO.
Drive
12
16
20
2
4
6
8
1.2 V
X
X
1.5 V
X
X
8-11
V
1.8 V
CCIO
X
X
X
X
CCIO
CCIO.
Voltages
Table 8-7 shows the drive strength available
2.5 V
X
X
X
X
X
LatticeECP/EC and LatticeXP
3.3 V
X
X
X
X
X
sysIO Usage Guide
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