LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 467

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 21-10. Select FPGA Device
b. Advanced SPI Flash Programming
i. Under Device Access Options, select Advanced SPI FLASH Programming, as shown in
ii. The FPGA Loader Setup Dialog will be launched.
iii. Click on CPLD or FPGA Device. It should look similar to Figure 21-10.
iv. The default Soft IP will automatically be added as the FPGA Loader Application Specific
v. Under Operation, select Fast Program.
vi. Click on Configuration Data Setup (see Figure 21-11).
vii. Under Configuration Data File, click on Browse to locate the user configuration file created
Figure 21-4.
Data File. If you instantiated the Soft IP into your own design, click on the Browse button to
select your bitstream. Clicking on the Default button will reload the default Soft IP bitstream.
using ispLEVER. Double-click on the file name. Use the Merging Multiple Configuration Data
Files option if you want to merge multiple bitstreams into the SPI Serial Flash device. Multiple
bitstreams would be used to configure multiple FPGAs using one SPI Serial Flash.
21-11
SPI Serial Flash Programming Using ispJTAG
on LatticeECP/EC FPGAs