LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 228
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Table 9-11. EBR-based FIFO and FIFO_DC Memory Port Definitions
Reset (or RST) only resets the output registers of the FIFO and FIFO_DC. It does not reset the contents of the
memory.
The various supported sizes for the FIFO and FIFO_DC in LatticeECP/EC and LatticeXP devices are shown in
Table 9-12.
Table 9-12. FIFO and FIFO_DC Data Widths Sizes for LatticeECP/EC and LatticeXP Devices
FIFO Flags
The FIFO and FIFO_DC have four flags available: Empty, Almost Empty, Almost Full and Full. The Almost Empty
and Almost Full flags have a programmable range.
The program ranges for the four FIFO flags are specified in Table 9-13.
Table 9-13. FIFO Flag Settings
The only restriction on the flag setting is that the values must be in a specific order (Empty=0, Almost Empty next,
followed by Almost Full and Full, respectively). The value of Empty is not equal to the value of Almost Empty (or
Full is equal to Almost Full). In this case, a warning is generated and the value of Empty (or Full) is used in place of
Almost Empty (or Almost Full). When coming out of reset, the Active High Flags empty and Almost Empty are set
to high, since they are true.
FIFO Attribute Name
AFF
AEF
Port Name in Generated
FF
EF
Module
CLKW
CLKR
FIFO Size
RST
CLK
512 x 18
256 x 36
WE
DO
RE
FF
AF
EF
AE
DI
8K x 1
4K x 2
2K x 4
1K x 9
Almost empty setting
Almost full setting
Full flag setting
Empty setting
Description
Clock (FIFO)
Read Port Clock (FIFO_DC)
Write Port Clock (FIFO_DC)
Write Enable
Read Enable
Reset
Data Input
Data Output
Full Flag
Almost Full Flag
Empty Flag
Almost Empty
Description
Input Data
DI[17:0]
DI[35:0]
DI[1:0]
DI[3:0]
DI[8:0]
9-29
DI
Programming Range
1 to (FF-1)
1 to (FF-1)
LatticeECP/EC and LatticeXP Devices
2N - 1
0
Rising Clock Edge
Rising Clock Edge
Rising Clock Edge
Active High
Active High
Active High
—
—
Active High
Active High
Active High
Active High
Output Data
DO[17:0]
DO[35:0]
DO[1:0]
DO[3:0]
DO[8:0]
DO
Memory Usage Guide
Program Bits
14
14
14
5
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