LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 345

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 12-7. Asynchronous Usage of Slave Parallel Configuration Mode
Figure 12-7 shows the Asynchronous peripheral write sequence using the Bypass option. To send configuration
data to a device, the WRITEN signal has to be asserted. During the write cycle, the BUSY signal provides hand-
shaking between the host system and the LatticeECP/EC device. When the BUSY signal is low, the device is ready
to read a byte of data at the next rising edge of CCLK. The BUSY signal is set high when the device reads the data
and the device requires extra clock cycles to process the data.
The CSN or CS1N signals can be used to temporarily stop the write process by setting either to a high state if the
host system is busy. The LatticeECP/EC device will resume the configuration when the both CSN and CS1N sig-
nals are set low again.
ispJTAG Mode
The LatticeECP/EC device can be configured through the ispJTAG port. The JTAG port is always on and available,
regardless of the configuration mode selected. The NONE mode (1) can be selected in the Lattice design software
to say that the JTAG port will be used exclusively, but is not required.
ISC 1532
Configuration through the JTAG port conforms to the IEEE 1532 Standard. The Boundary Scan cells take control of
the I/Os during any 1532 mode instruction. The Boundary Scan cells can be set to a pre-determined values when-
ever using the JTAG 1532 mode. Once configuration is complete, an internal Done bit is set, which will release the
DONE pin.
Transparent Read Back
The ispJTAG transparent read back mode allows the user to read the content of the device while the device
remains in a functional state. The I/O and non-JTAG configuration pins remain active during a Transparent Read
Back. The device will enter the Transparent Read Back mode through a JTAG instruction. The user must ensure
ispJTAG (1149.1 interface)
PROGRAMN
Mode
WRITEN
CLOCK
DONE
D[0:7]
BUSY
INITN
PROGRAMN
CCLK
D[0:7]
DONE
INITN
BUSY
WRITEN
CSN
CS1N
(Asynchronous)
Lattice FPGA
Slave Parallel
CFG[2]
X
DOUT
CFG2
CFG1
CFG0
12-12
CFG[1]
X
LatticeECP/EC sysCONFIG Usage Guide
CFG[0]
X
CCLK
DI
DONE
INITN
PROGRAMN
Lattice FPGA
Slave Serial
Any CONFIG_MODE or NONE1
CONFIG_MODE Parameter
DOUT
CFG0
CFG2
CFG1