LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 343

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 12-5. Master and Slave Serial Daisy Chained
Slave Serial Mode
Slave Serial Mode is the default mode for configuration in the Lattice design software. In Slave Serial mode the
CCLK pin becomes an input and will receive the incoming clock. The device accepts the data at DI on the rising
edge of CCLK. After the device is fully configured, if the Bypass option has been set, data sent to DI will be pre-
sented to the next device on the DOUT pin as shown in Figure 12-5.
Master Parallel Mode
Configuration using Master Parallel Mode is used to work together with a parallel port PROM without additional
external logic. When Master Parallel Mode is chosen, the device will generate CCLK as specified by the
MCLK_FREQ preference. The CCLK signal is used to provide a programming clock to the PROM and slave
devices. Data is transferred byte wide to the D[0:7] pins. The WRITEN pin must be held low to write to the device. If
an overflow option is not selected, the CSN and CS1N pins must be driven low to enable configuration and read
back.
The Master Parallel Mode can support two types of overflow, Bypass and Flow Through. If the Bypass option is set,
the data presented to the D[0:7] pins will be serialized and bypassed to the DOUT pin when the configuration is
complete. If the Flow Through option is set, upon completion of the configuration, the CSOUT signal will drive the
following Parallel Mode device chip select as shown in Figure 12-6.
If either overflow option is selected, the CSN or CS1N pins can be toggled to reset the Master Parallel device out of
the Overflow option, otherwise both chip select pins should be held low to keep the device active for configuration.
Slave Serial (no overflow option)
Slave Serial (Bypass On)
Master Parallel (no overflow option)
Master Parallel (Bypass ON)
Master Parallel (Flow Through ON)
RESET/OE
PROM
Mode
Mode
DATA
CLK
CS
10K
CCLK
DI
DONE
INITN
PROGRAMN
Master Serial
Lattice FPGA
CFG[2]
CFG[2]
1
1
1
1
1
DOUT
CFG2
CFG0
CFG1
12-10
CFG[1]
CFG[1]
1
1
0
0
1
LatticeECP/EC sysCONFIG Usage Guide
CFG[0]
CFG[0]
1
1
0
0
0
DI
CCLK
DONE
INITN
PROGRAMN
MASTER_PARLLEL
MASTER_PARLLEL_BYPASS
MASTER_PARLLEL_FLOWTHR
SLAVE_SERIAL (Default)
SLAVE_SERIAL_BYPASS
Lattice FPGA
Slave Serial
CONFIG_MODE Parameter
CONFIG_MODE Parameter
CFG2
CFG1
CFG0
DOUT