LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 412

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 17-3. Interface Timing Preference File Example
Analyzing Timing Reports
This section describes two examples of actual Trace reports (.twr report file from Trace). The purpose is to analyze
both examples and understand each section of the reports given the design paths constrained.
Example 1. Multicycle Between Two Different Clocks
In this first example, CLKA and CLKB were assigned 104 MHz and 66 MHz frequencies respectively.
In addition, a multicycle constraint was specified as per the preference file:
See Figure 17-4 for the block diagram and waveform for this example. The resulting Trace report is shown in
Figure 17-5.
Figure 17-4. Multicycle Clock Domains Block Diagram and Waveform
FREQUENCY
FREQUENCY NET "CLKB" 66 MHZ ;
MULTICYCLE "M2" START CLKNET "CLKA" END CLKNET "CLKB" 2.000000 X ;
CLKA
CLKB
PERIOD PORT "clk" 30 NS ;
INPUT_SETUP "port_controller*" 9 NS HOLD 3 NS CLKNET "clk";
CLOCK_TO_OUT "port_controller*" 18 NS MIN 3 NS CLKNET "clk";
OUTPUT PORT "port_controller*" LOAD 74 PF ;
TEMPERATURE 96.8 C ;
NET "CLKA" 104 MHZ ;
CLKB
CLKA
7.9 ns
7.7ns
15.15 ns
9.60 ns
7.70 ns
7.90 ns
30.30 ns
17-6
Combinational
Logic
Lattice Semiconductor FPGA
Successful Place and Route