LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 400

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
By controlling the placement of specified logic elements, design floorplanning methodologies help designers meet
the requirements of large system design.
Floorplanning Design Flow
In both traditional and floorplanning FPGA design flows, the designer divides the system into modules. The mod-
ules can be individual circuits, parts of circuits, or parts of the design hierarchy. After module design and optimiza-
tion, the designer integrates the modules into the system. Finally, the designer tests and optimizes the system.
In the traditional flow, the system may not meet performance requirements even if each module meets the require-
ments before integration. Even when timing requirements have been satisfied, changes to one module can affect
the performance of others. Re-optimizing modules to meet system performance results in many design iterations.
Floorplanning methodologies assist in the design, testing, and optimization of each individual module while retain-
ing the optimized characteristics of the individual modules. Module integration into the system requires only system
optimization between modules. The floorplanning methodologies provide additional flexibility by allowing the isp-
LEVER software to automatically place defined modules, or allowing the user to control the placement of specific
modules, which provide performance preservation and optimization.
When to Floorplan
Floorplanning methodologies are intended to assist users who require some degree of handcrafting for their
designs. The designer must understand both the details of the device architectures and the ways floorplanning can
be used to refine a design. Successful floorplanning is very much an iterative process and it can take time to
develop a floorplan that outperforms an automatic, software processed design. Because of the nature of floorplan-
ning and its interaction with the automatic MAP and PAR software tools, several prerequisites are necessary in
order to floorplan a design successfully.
For Lattice Semiconductor FPGAs, the general rule-of-thumb is that floorplanning should be considered when the
performance needed cannot be met and routing delays account for over 60% of the critical path delays. That is,
interacting components are too far apart in the FPGA array to achieve short routing delays. This has shown to be a
problem especially with large designs in high density FPGAs because of the possibilities of long distance routes.
As programmable logic design densities continue to escalate beyond 100,000 gates, traditional design flow —
design entry to synthesis to place and route — will sometimes not yield predictable, timely, and optimized results.
Note that the guidelines discussed above only apply to designs that have been routed by the software for several
routing iterations. The default number of routing iterations via the ispLEVER Project Navigator is variable depend-
ing on the Lattice Semiconductor FPGA device family chosen.
A note on delays: Path delays in programmable devices are made up of two parts: logical delays and routing
delays. Logical delays in this context are delays through components, such as a a programmable function unit
(PFU), a programmable input/output (PIO), a slice, or an embedded function (i.e. a block RAM, PLL, or embedded
FPSC ASIC). The routing delay is the delay of the interconnect between components. Figures 1 and 2 show delay
examples from timing wizard report files (.twr).
• Use of IP blocks
• Reuse of previously optimized design elements
• Detailed knowledge of the specifics of the target architecture and device
• Detailed knowledge of the specifics of the design being implemented
• A design that lends itself to floorplanning
• A willingness to iterate a floorplan to achieve the desired results
• Realistic performance and density goals
16-2
Lattice Semiconductor Design Floorplanning