LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 309
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
Revision History
September 2006
December 2004
October 2004
January 2005
October 2005
June 2004
June 2007
April 2007
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
Date
Version
01.0
01.1
02.0
03.0
04.0
04.1
04.2
04.3
Initial release.
RST description with timing diagram added.
Primitive ‘Wake_On_Lock’ removed.
Added RST input in EPLLB.
Fin min 33 replaced with 25.
FB_MODE default = CLOCKTREE
CLKOP_DIV values for EHXPLLB 2, 4, 8,16, 32.
Appendices C and D integrated to body of the document.
DCS source code example moved to Appendix A.
LatticeXP information added.
Figures 6 and 7 updated.
CLKOP_FREQ, CLKOK_FREQ user attributes added.
FB_MODE added.
Clock Distribution section added.
Example code section removed and referred to help file.
GUI screen shots updated.
MM/IP Manager renamed as IPexpress.
Epllb definition section removed.
Clkos/clkok select attributes added.
Detailed clock distribution information added.
Updated footnote 3 in the LatticeECP/EC and LatticeXP PLL Attributes
table.
Updated Lock Output section of PLL Inputs and Outputs..
LatticeECP/EC and LatticeXP PLL I/O Definitions table - corrected sig-
nal name DDAIDEL to read DDAIDEL[2:0] in the Signals column.
11-19
sysCLOCK PLL Design and Usage Guide
Change Summary
LatticeECP/EC and LatticeXP
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