LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 337

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
LatticeECP/EC sysCONFIG Usage Guide
CSN and CS1N
Both CSN and CS1N are active low control input pins. When CSN OR CS1N are high, D[0:7] and BUSY pins are
tri-stated. When the CSN and CS1N pins are both high, they will reset the flow-through/bypass register. CSN and
CS1N are interchangeable when controlling the D[0:7], INITN and BUSY pins.
WRITEN
The WRITEN pin is an active low control input pin. The WRITEN pin is used to determine the direction of the data
pins D[0:7]. The WRITEN pin is driven low when a byte of data is to be shifted into the device during programming.
The WRITEN pin will be driven high when data is to be read from the device through a parallel configuration mode.
The WRITEN pin is not used for serial configuration modes.
BUSY/SISPI
The BUSY/SISPI pin is a dual function pin. In the parallel configuration mode, the BUSY pin is a tri-stated output.
The BUSY pin will be driven low by the device only when it is ready to receive a byte of data at D[0:7] pins or a byte
of data is ready for reading. The BUSY pin can be used to support asynchronous peripheral mode. This is to
acknowledge that the device might need extra time to execute a command.
In the SPI configuration modes, the BUSY/SISPI pin becomes an output pin that drives read control data back to
the SPI memory.
ispJTAG Pins
The ispJTAG pins are the standard IEEE 1149.1 TAP pins. The ispJTAG pins are dedicated pins and are always
accessible when the LatticeECP/EC device is powered up. In addition, the dedicated sysCONFIG pins such as the
DONE pin as described in the Dual-Purpose Control Pins section of this document are also available when using
LatticeECP/EC ispJTAG pins. The dedicated sysCONFIG pins are not required for JTAG operation, but may be
useful at times.
TDO
The Test Data Output pin is used to shift out serial test instructions and data. When TDO is not being driven by the
internal circuitry, the pin will be in a high impedance state.
TDI
The Test Data Input pin is used to shift in serial test instruction and data. An internal pull-up resistor on the TDI pin
is provided. The internal resistor is pulled up to V
CCJ.
TMS
The Test Mode Select pin controls test operations on the TAP controller. On the falling edge of TCK, depending on
if TMS is high or low, a transition will be made in the TAP controller state machine. An internal pull-up resistor on
the TMS pin is provided. The internal resistor is pulled up to V
CCJ.
TCK
The test clock pin TCK provides the clock to run the TAP controller, loading and reloading the data and instruction
registers. TCK can be stopped in either the high or low state and can be clocked at frequencies up to the frequency
indicated in the device data sheet. The TCK pin supports hysteresis, with the value shown in the DC parameter
table of the LatticeECP/EC Family Data Sheet.
Optional TRST
The JTAG Test Reset pin TRST in not supported in the LatticeECP/EC devices.
V
CCJ
JTAG V
supplies independent power to the JTAG port to allow chaining with other JTAG devices at a common
CC
voltage.
Configuration and JTAG Pin Physical Description
All of the control pins and programming bus default to LVCMOS. The bank V
pin determines the voltage level of
CCO
the sysCONFIG pins. The JTAG pin voltage levels are determined by the V
pin voltage level. Controlling the
CCJ
12-4