LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 461

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Schematic
The schematic in Figure 21-2 illustrates how to wire the ispJTAG connector, FPGA, and SPI Serial Flash.
Figure 21-2. Hardware Schematic
• The download header has standard 0.1 inch pin-to-pin spacing.
• The 4.7K pull-down resistors prevent spurious clock pulses during V
• The CCLK frequency can be as high as 50MHz, so keep this trace fairly short.
• V
• During configuration CCLK drives the SPI Serial Flash CLK pin, but once the FPGA completes configura-
• In addition to standard decoupling practices, place a decoupling capacitor close to the connector’s V
to their clock line to keep the stub length as short as possible.
(today that voltage is 3.3V but this will change over time as Flash chip geometries decrease). For all pack-
ages these signals are located in bank 3.
tion CCLK goes into tri-state. The CCLK pin is not accessible by user code so CCLK needs to be wired to a
nearby General Purpose I/O pin (GPIO) to allow the FPGA fabric to supply a clock to the SPI Serial Flash.
This pin is part of the Soft SPI Interface and is unique to each package. If the user embeds the Soft SPI
Interface into their code then this pin, along with the other pins wired to the SPI Serial Flash, must be locked
using the Pre-Map Preference Editor in ispLEVER. A complete list of these pins is found in Table 21-5.
pin. Any standard ceramic capacitor value may be used, for example 0.1 µF, 0.01 µF, etc.
CCIO
for the bank that drives the signals to the SPI Serial Flash must match the SPI Serial Flash V
3.3V
10K
1x10
10
1
2
3
4
5
6
7
8
9
/HOLD
/WP
V
TDO
TDI
TMS
DONE
TCK
INITN
SPI Serial
CCJ
Flash
CLK
/CS
DO
DI
4.7K
(Optional)
(Optional)
4.7K
21-5
SPI Serial Flash Programming Using ispJTAG
* In SPIX mode only, SPID0
connects to DO and a resistor
** This pin is unique for each
package, see information below
TDO
TDI
TMS
TCK
DONE
INITN
GPIO
CCLK
CSSPI
SISPI
SPIDO
LatticeECP/EC
**
SPID0*
SPID7
SPID6
SPID5
SPID4
SPID3
SPID2
SPID1
CFG2
CFG1
CFG0
CC
ramp-up. Place the resistors close
SPI = ‘000’
SPIX = ‘001’
on LatticeECP/EC FPGAs
10K
SPIX Only
pull-up or
down as
required
3.3V
SPIX
Only
CC
CCJ