LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 289

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LFEC3E-3QN208I

Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r

Specifications of LFEC3E-3QN208I

Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix F. DDR400 Interface using the LatticeEC Evaluation Board
The DDR400 interface was implemented using the LatticeEC20 device on the LatticeEC Advanced Evaluation
Board. Figures 10-21, 10-22 and 10-23 show the READ, WRITE and WRITE to READ transition operations running
at 200MHz. For more information on the evaluation board, refer to LatticeEC Advanced Evaluation Board User’s
Guide available on the Lattice web site at www.latticesemi.com.
Figure 10-21. READ Function Running at 200MHz
Note: An extra READ command is implemented in the LatticeEC20 device to protect the data during postamble.
This extra READ is not required for other LatticeEC devices. Refer to the DQS Postamble section of this document
for more information.
10-36

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