LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 473

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 21-15. Select Pre-Map Preference Editor
This will start the editor; it should look similar to Figure 21-16. The Pre-Map Preference Editor is where pin num-
bers and other attributes are assigned to the various I/O in a design. Figure 21-16 shows the proper pin selection
for a 484 fpBGA, it also shows proper selection of the I/O type (in this case LVCMOS_3.3). Each package requires
a different pin selection; refer to Table 21-5 and the schematic in Figure 21-2 (in the Hardware section of this docu-
ment) for details.
While it is recommended that the pin listed in Table 21-5 be used as the GPIO to wire to CCLK, if the Soft IP is
instantiated into the user design then any pin can be selected - with the following cautions:
1. The Default Soft IP is built to use the default pin (see step 5 above under Programming Procedures), if a
2. Do not select the DOUT pin as the GPIO to wire to CCLK. DOUT is an output during configuration, as is
3. Select a pin from a bank that has its V
different pin is chosen the Default Soft IP will not work, i.e. you must instantiate the Soft IP in your design.
CCLK. Selecting DOUT will cause contention.
CCIO
connected to 3.3V.
21-17
SPI Serial Flash Programming Using ispJTAG
on LatticeECP/EC FPGAs