LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 457

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

October 2005
Introduction
Like all SRAM FPGAs the LatticeECP™ and LatticeEC™ devices need to be configured at power-up. This configu-
ration can be done via:
If a boot memory is desired the SPI approach provides a number of advantages over traditional FPGA boot mem-
ory:
Like all boot memories, SPI Serial Flash needs to be loaded with the FPGA configuration data. There are three
options for programming an SPI memory used in conjunction with a LatticeECP/EC device. The SPI memory can
be configured off-board using a stand-alone programmer, the memory can be programmed on-board using its SPI
interface, or the memory can be programmed on-board via JTAG through the LatticeECP/EC device.
This technical note details the on-board configuration of SPI memory via the JTAG interface.
Related Documents
The following documents are available for download from the Lattice web site at www.latticesemi.com.
Hardware and Software Requirements
SPI/SPIX Differences
The majority of SPI Serial Flash on the market support a common read Operation Code (Op Code). LatticeECP/EC
devices offer direct connection to these devices by hardwiring the read Op Code (03H) into the FPGA silicon.
These devices are sometimes referred to as SPI3 devices because they support this common Read Op Code.
SPIX mode allows the LatticeECP/EC to easily interface to SPI Serial Flash devices that support a different read
Op Code. This can be done with pull-up and pull-down resistors on the PCB wired to the SPID[7:0] pins, telling the
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1. Serial Peripheral Interface (SPI) boot memory
2. Traditional FPGA boot memory
3. JTAG
4. Microprocessor interface
1. SPI devices are available from multiple vendors ensuring stable supply
2. The cost of SPI memory is up to 75% less than traditional FPGA boot memory
3. SPI memory is available in space saving 8-pin packages that are considerably smaller than packages used
• LatticeECP & EC – Low-Cost FPGA Configuration via Industry-Standard SPI Serial Flash
• LatticeECP/EC Family Handbook
• Lattice technical note TN1053, LatticeECP/EC sysCONFIG™ Usage Guide
• ispDOWNLOAD
• An ispDOWNLOAD Cable, either USB or Parallel. Refer to the ispDOWNLOAD Cable Data Sheet for part
• Properly installed ispLEVER
• Properly installed ispVM
numbers
for traditional FPGA boot memory
®
Cable Data Sheet
®
System 14.3 or later
SPI Serial Flash Programming Using
®
4.2 or later
ispJTAG on LatticeECP/EC FPGAs
21-1
Technical Note TN1078
tn1078_04.0