LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 459

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
SPI Serial Flash Interface
The standard pin-out for 8-pin SPI Serial Flash memories is shown below (top view):
Figure 21-1. 8-Pin SPI Flash Memory, Standard Pinout
Note: V
that voltage is 3.3V but this will change over time as Flash chip geometries decrease). For all LatticeECP/EC pack-
ages these signals are located in bank 3.
The SPI interface is a 4-wire serial interface comprised of the following signals:
The SPI interface also supports the following two functions:
Note: The LatticeECP/EC SPI interface supports the basic 4-wire interface, but the user is free to implement these
additional functions if desired.
ispJTAG Interface
The ispJTAG interface supports both IEEE 1149.1 Boundary Scan and IEEE 1532 In-System Configuration. Stan-
dard pinouts for 1x10, 1x8, and 2x5 download headers are shown in Table 21-4. The 1x10 header is preferred but
ultimately the header chosen will depend on the available download cable. All new download cables have uncom-
mitted “flywire” connections, so they can be attached to any of the header styles. Direction, in Table 21-4, refers to
the cable, for example “output” indicates an output from the cable to the FPGA.
1. CS – Chip Select, Input: Enables and disables device operation. When high the device is at standby
2. CLK – Serial Clock, Input: Provides timing for the interface. The Serial Data Input (DI) is latched on the
3. DI – Serial Data In, Input: When the device is enabled (CS is low) this pin allows instructions, addresses,
4. DO – Serial Data Out, Output: When the device is enabled (CS is low) this pin allows data and status to
1. HOLD – Input: Allows device to be paused without de-selecting it. When HOLD is low DO will be tri-stated
2. WP – Write Protection, Input: Used to prevent inadvertent writing of the Status Register Block Protect
CCIO
power levels and the output is tri-stated. When low the device powers up and instructions can be written to
and data read from the device.
rising edge of CLK. Serial Data Output (DO) changes after the falling edge of CLK.
and data to be serially written to the device. Data is latched on the rising edge of the CLK.
be serially read from the device. Data is shifted out on the falling edge of the CLK.
while DI and CLK are ignored. This function is useful when multiple devices are sharing the same SPI sig-
nals.
bits.
for the bank that drives the signals to the SPI Serial Flash must match the SPI Serial Flash V
GND
WP
DO
CS
1
2
3
4
21-3
SPI Serial Flash Programming Using ispJTAG
8
7
6
5
VCC
HOLD
CLK
DI
on LatticeECP/EC FPGAs
CC
(today