LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 304
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFEC6/LFXP6 and smaller devices have limited routing resources and can implement a maximum of nine second-
ary clocks per device.
Figure 11-11. Primary Clock and Secondary Clock/CE/LSR Distribution
Dynamic Clock Selection (DCS)
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock
sources and avoids glitches or runt pulses on the output clock, regardless of when the enable signal is toggled. The
DCS blocks are located in pairs at the center of each side of the device. Thus, there are eight of them in every
device.
Table 11-5. DCS I/O
Primary Clock Net
Secondary Clock/CE/LSR Net
Input
Output
PCLK0
PCLK1
PCLK2
PCLK3
SCLK0/CE/LSR
SCLK1/CE/LSR
SCLK2/CE/LSR
SCLK3/CE/LSR
I/O
SEL
CLK0
CLK1
DCSOUT
Name
Primary Clock
11-14
Secondary Clock
Secondary Clock
Secondary Clock
Input Clock Select
Primary Clock Input 0
Primary Clock Input 1
To Primary Clock
Local
Local
/CE/LSR
/CE/LSR
/CE/LSR
sysCLOCK PLL Design and Usage Guide
Local
3
4
Description
3
3
LatticeECP/EC and LatticeXP
CLK(0:3)
CE(0:3)
LSR(0:3)
PFU
PFU
PFU
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