LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 377

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

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Lattice Semiconductor
LatticeECP-DSP sysDSP Usage Guide
property REG_PIPELINE0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE2_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE2_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE2_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE3_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE3_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE3_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_OUTPUT_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_OUTPUT_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_OUTPUT_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_SIGNEDAB_0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_SIGNEDAB_0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_SIGNEDAB_0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_SIGNEDAB_1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_SIGNEDAB_1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_SIGNEDAB_1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ADDNSUB1_0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_ADDNSUB1_0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_ADDNSUB1_0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ADDNSUB1_1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_ADDNSUB1_1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_ADDNSUB1_1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ADDNSUB3_0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_ADDNSUB3_0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_ADDNSUB3_0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_ADDNSUB3_1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_ADDNSUB3_1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_ADDNSUB3_1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property SHIFT_IN_A0 {“FALSE”, “TRUE”};
property SHIFT_IN_B0 {“FALSE”, “TRUE”};
property SHIFT_IN_A1 {“FALSE”, “TRUE”};
property SHIFT_IN_B1 {“FALSE”, “TRUE”};
property SHIFT_IN_A2 {“FALSE”, “TRUE”};
property SHIFT_IN_B2 {“FALSE”, “TRUE”};
property SHIFT_IN_A3 {“FALSE”, “TRUE”};
property SHIFT_IN_B3 {“FALSE”, “TRUE”};
property GSR {“ENABLED”,”DISABLED”};
MULT9X9 Primitive
MULT9X9(CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3,SIGNEDAB,
A0,A1,A2,A3,A4,A5,A6,A7,A8,B0,B1,B2,B3,B4,B5,B6,B7,B8,
SRIA0,SRIA1,SRIA2,SRIA3,SRIA4,SRIA5,SRIA6,SRIA7,SRIA8,
SRIB0,SRIB1,SRIB2,SRIB3,SRIB4,SRIB5,SRIB6,SRIB7,SRIB8,
SROA0,SROA1,SROA2,SROA3,SROA4,SROA5,SROA6,SROA7,SROA8,
SROB0,SROB1,SROB2,SROB3,SROB4,SROB5,SROB6,SROB7,SROB8,
P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16,P17) is black-box
{
property REG_INPUTA_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTA_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTA_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTB_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTB_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTB_RST {“RST0”,”RST1”,”RST2”,”RST3”};
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