LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 406

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
With Lattice Semiconductor FPGAs, floorplanning is an optional methodology to help designers improve perfor-
mance and density of a fully, automatically placed and routed design. Floorplanning is particularly useful on struc-
tured designs and data path logic.
Design floorplanning is very powerful and provides a combination of automation and user control for design reuse
and modular, hierarchical, and incremental design flows. It advances the design of large systems on FPGAs. It pro-
vides the designer with capabilities in the management and optimization of large systems. Its multifaceted capabil-
ities result in shortened design cycles and faster time to market.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
• Correct floorplanning can increase logic element count slightly.
• Completed floorplanning should be annotated into the HDL.
• Floorplanning enhances the reusability of designs by keeping placement directives in the HDL.
• Use PGROUPs for physical grouping in the same hierarchy.
• Use UGROUPs for logical grouping across hierarchies.
[phone] (Outside North America)
[e-mail]
16-8
Lattice Semiconductor Design Floorplanning