LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 6

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide
Generic High Speed DDR Implementation .................................................................................................... 10-17
Board Design Guidelines ............................................................................................................................... 10-17
References..................................................................................................................................................... 10-18
Technical Support Assistance........................................................................................................................ 10-18
Revision History ............................................................................................................................................. 10-18
Appendix A. Using IPexpress™ to Generate DDR Modules.......................................................................... 10-19
Appendix B. Verilog Example for DDR Input and Output Modules ................................................................ 10-21
Appendix C. VHDL Example for DDR Input and Output Modules.................................................................. 10-23
Appendix D. Generic (Non-Memory) High-Speed DDR Interface .................................................................. 10-28
Appendix E. List of Compatible DDR SDRAM ............................................................................................... 10-32
Appendix F. DDR400 Interface using the LatticeEC Evaluation Board.......................................................... 10-35
Introduction ...................................................................................................................................................... 11-1
Features ........................................................................................................................................................... 11-1
Functional Description...................................................................................................................................... 11-1
LatticeECP/EC and LatticeXP PLL Primitive Definitions.................................................................................. 11-4
PLL Usage in IPexpress................................................................................................................................... 11-7
Equations for Generating Input and Output Frequency Ranges .................................................................... 11-10
Clock Distribution in LatticeECP/EC and LatticeXP ....................................................................................... 11-11
Clock Net Preferences ................................................................................................................................... 11-12
Dynamic Clock Selection (DCS) .................................................................................................................... 11-14
Other Design Considerations ......................................................................................................................... 11-17
DCS Usage with VHDL .................................................................................................................................. 11-18
Technical Support Assistance........................................................................................................................ 11-19
Revision History ............................................................................................................................................. 11-19
Appendix A. Clock Preferences ..................................................................................................................... 11-20
FCRAM (Fast Cycle Random Access Memory) Interface..................................................................... 10-17
DDR Generic......................................................................................................................................... 10-19
DDR Memory Interface ......................................................................................................................... 10-20
VHDL Implementation ........................................................................................................................... 10-28
Verilog Example .................................................................................................................................... 10-30
Preference File...................................................................................................................................... 10-31
PLL Divider and Delay Blocks................................................................................................................. 11-1
PLL Inputs and Outputs .......................................................................................................................... 11-2
PLL Attributes.......................................................................................................................................... 11-3
PLL Attributes Definitions........................................................................................................................ 11-4
Dynamic Delay Adjustment ..................................................................................................................... 11-6
Including sysCLOCK PLLs in a Design................................................................................................... 11-7
IPexpress Usage..................................................................................................................................... 11-7
EHXPLLB Example Projects ................................................................................................................... 11-9
f
f
Primary Clock Sources and Distribution................................................................................................ 11-11
Primary-Pure and Primary-DCS............................................................................................................ 11-12
Global Primary Clock and Quadrant Primary Clock .............................................................................. 11-12
Secondary Clock Sources and Distribution........................................................................................... 11-13
Limitations on Secondary Clock Availability.......................................................................................... 11-13
DCS Waveforms ................................................................................................................................... 11-15
Use of DCS with PLL ............................................................................................................................ 11-17
Jitter Considerations ............................................................................................................................. 11-17
Simulation Limitations ........................................................................................................................... 11-17
PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available ................. 11-18
DCS Usage with Verilog........................................................................................................................ 11-18
ASIC...................................................................................................................................................... 11-20
VCO
PFD
Constraint ...................................................................................................................................... 11-10
Constraint ..................................................................................................................................... 11-10
5
LatticeECP/EC Family Data Sheet
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