LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 336

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
LatticeECP/EC sysCONFIG Usage Guide
released. An open drain DONE pin can be held low externally and, depending on the wake-up sequence selected,
the device will not become functional until the DONE pin is released.
CCLK
The CCLK pin is a bi-directional pin. The direction depends on whether a Master Mode or Slave Mode is selected.
If a Master Mode is selected when the CFG pins are sampled, the CCLK pin will become an output pin; otherwise
CCLK will become an input pin. If the CCLK pin becomes an output pin, the internal programmable oscillator is
connected to the CCLK and is driven out to slave devices. CCLK will stop 120 clocks cycles after the DONE pin is
brought high and the device wake-up sequence completed. The extra clock cycles are provided to ensure that
enough clock cycles are provided to wake up other devices in the chain. When stopped, CCLK will become tri-
stated as an input. The CCLK will restart on the next configuration initialization sequence, such as the PRO-
GRAMN pin being toggled. The MCCLK_FREQ Parameter controls the CCLK Master frequency. See the Master
Clock Selection section of this document for more information. For Serial and Parallel Slave modes, it is recom-
mended that CCLK is continuously active during configuration and error recovery sequence.
Dual-Purpose sysCONFIG Pins
The following is a list of dual-purpose sysCONFIG pins. If any of these pins are used for configuration and user I/O,
the user must adhere to the requirements listed above in the section entitled Configuration Pins.
DI/CSSPIN
The DI/CSSPIN dual-purpose pin is designated as DI (Data Input) for all of the serial bit stream configurations,
such as Slave Serial. DI has an internal weak pull up.
In either SPI or SPIX mode, the DI/CSSPIN becomes the dedicated Chip Select output to drive the SPI Flash chip
select. CSSPIN will drive high when the LatticeECP/EC device is not in the process of configuration through the
SPI Port.
D[0:7]/SPID[7:0]
The D[0:7] pins support both the SPI mode and Parallel configuration modes. In the Parallel configuration modes,
the D[0:7] pins are tri-stated bi-directional I/O pins used for parallel data write and read. A byte of data is driven into
or read from these pins. When the WRITEN signal is low and the CSN and CS1N pins are low, the D[0:7] pins will
become an input. When the WRITEN signal is driven high and the CSN and CS1N pins are low, the pins become
output pins for reading. The PERSISTENT preference must be set to support read back to preserve the D[0:7] pins
so the device can monitor for the read back instruction. The CSN and CS1N pins will enable the Data D[0:7] pins.
In SPI mode, the D[0:7]/SPID[7:0] pins become individual inputs for one or more SPI memory outputs. If more than
one SPI memory is used, SPI memory zero output will be wired to D7/SPID0, SPI memory one output will be wired
to D6/SPID1, the data fed to these pins will be interleaved and then sent to the internal configuration engine. For
SPIX Mode, the D[0:7]/SPID[7:0] pins will also support sampling of external resistors for determining the Read Op
Code.
DOUT/CSON
The DOUT/CSON pin is an output pin and has two purposes. For serial and parallel configuration modes, when the
BYPASS mode is selected, this pin will become DOUT. When the device in BYPASS becomes fully configured, a
BYPASS instruction will be executed and the data on DI or D[0:7] will then be presented to the DOUT pin through a
bypass register to serially pass the data to the next device. In a parallel configuration mode D0 will be shifted out
first followed by D1, D2, and so on.
For parallel configuration modes, when the FLOW_THROUGH mode is selected, this pin will become the Chip
Select OUT (CSON). In the FLOW_THROUGH mode, when the device is fully configured, the Flow Through
instruction will be executed and the CSON pin will be driven low to enable the next device chip select pin.
The DOUT/CSON bypass register will drive out a HIGH upon power up and continue to do so till the execution of
the Bypass/Flow Through instruction within the bit stream.
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