LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 302
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Note on the Primary Clock
The CLKOP must be used as the feedback source to optimize the PLL performance.
Most designers use the PLL for the clock tree injection removal mode and the CLKOP should be assigned as the
primary clock. This is done automatically by the software unless the user specifies otherwise.
CLKOP can route to CLK0 and CLK1 only. CLKOS/CLKOK can route to all primary clocks (CLK0 to CLK3).
When CLK2 or CLK3 is used as a primary clock and there is only one clock input to the DCS, the DCS is assigned
as a buffer mode by the software. Please see the DCS section of this document for further information.
Clock Net Preferences
There are two clock nets, primary clock and secondary clock.
As illustrated in Figure 11-9, users can set each clock to the desired clock net in the Pre-map Preference Editor or
write in the Preference File as shown in the examples below.
Primary-Pure and Primary-DCS
Primary Clock Net can be assigned to either Primary-Pure (CLK0 and CLK1) or Primary-DCS (CLK2 and CLK3).
Syntax Example
Global Primary Clock and Quadrant Primary Clock
Global Primary Clock
If a primary clock is not assigned as a quadrant clock, the software assumes it is a Global Clock.
There are two Global Primary/Pure Clocks and two Global Primary/DCS Clocks available.
Quadrant Primary Clock
Any Primary Clock may be assigned to a Quadrant Clock. The Clock may be assigned to a single quadrant or to
two adjacent quadrants (not diagonally adjacent).
When the quadrant clock net is used, users must ensure that the registers each clock drives can be assigned in
that quadrant without any routing issues.
With the Quadrant Primary Clocking scheme, the maximum number of Primary Clocks is 16 as long as all the Pri-
mary Clock Sources are avaialble.
Syntax Example
USE PRIMARY DCS NET "bf_clk";
USE PRIMARY PURE NET "bf_clk" QUADRANT_TL;
11-12
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP
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