LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 311
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 311 of 478
- Download datasheet (13Mb)
Lattice Semiconductor
Physical Path Details:
If CLKPORT is used, the trace is complete back to the clock port resource and provides PLL compensation timing
numbers.
The above preference will yield the following clock path:
Clock path RxClk to PFU_33:
INPUT_SETUP
Specifies an setup time requirement for input ports relative to a clock net.
PLL_PHASE_BACK
This preference is used with INPUT_SETUP when the user wants a trace calculation based on the previous clock
edge.
This preference is useful when setting the PLL output phase adjustment. Since there is no negative phase adjust-
ment provided, the PLL_PHASE_BACK preference works as if negative phase adjustment is available.
For example:
If phase adjustment of -90° of CLKOS is desired, the user can set the phase to 270° and set the INPUT_SETUP
preference with PLL_PHASE_BACK.
ROUTE
IN_DEL
ROUTE
MCLK_DEL
ROUTE
Name
Name
CLOCK_TO_OUT PORT "RxAddr_0" 6.000000 ns CLKPORT "RxClk" ;
INPUT_SETUP PORT "datain" 2.000000 ns HOLD 1.000000 ns CLKPORT "clk" PLL_PHASE_BACK ;
Clock path pll_inst/pll_utp_0_0 to PFU_33:
Fanout Delay (ns)
Fanout Delay (ns)
--------
--------
---
2.892 (0.0% logic, 100.0% route), 0 logic levels.
8.771 (57.4% logic, 42.6% route), 2 logic levels.
49
49
1
---
1.431
0.843
2.892
2.892
3.605 ULPPLL.CLKIN to
ULPPLL.MCLK to
ULPPLL.MCLK to
D5.PAD to
D5.INCK to ULPPLL.CLKIN RxClk_c
Site
Site
D5.INCK RxClk
R3C14.CLK0 pll_rxclk
R3C14.CLK0 pll_rxclk
ULPPLL.MCLK pll_inst/pll_utp_0_0
Resource
Resource
11-21
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP
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