LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 208
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
The Single Port RAM (RAM_DQ) can be configured as NORMAL, READ BEFORE WRITE or WRITE THROUGH
modes. Each of these modes affects what data comes out of the port Q of the memory during the write operation
followed by the read operation at the same memory location. The READ BEFORE WRITE attribute is supported for
x9, x18 and x36 data widths.
Additionally users can select to enable the output registers for RAM_DQ. Figures 8-7 through 8-12 show the inter-
nal timing waveforms for the Single Port RAM (RAM_DQ) with these options.
Figure 9-9. Single Port RAM Timing Waveform – NORMAL Mode, without Output Registers
ClockEn
Address
Clock
WrEn
Data
Q
t
t
SUADDR_EBR
SUDATA_EBR
t
SUCE_EBR
Data_0
Add_0
t
SUWREN_EBR
t
t
HADDR_EBR
HDATA_EBR
Invalid Data
Data_1
Add_1
t
HWREN_EBR
9-9
Add_0
LatticeECP/EC and LatticeXP Devices
t
CO_EBR
Data_0
Add_1
Memory Usage Guide
Data_1
Add_2
t
HCE_EBR
Data_2
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