LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 338

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
JTAG pin by V
In-System Programming Design Guidelines for ispJTAG Devices, available on the Lattice web site at www.lattices-
emi.com.
Configuration Modes
The LatticeECP/EC devices support many different types of configuration modes utilizing either serial or parallel
data inputs. On power-up or upon driving the PROGRAMN pin low, the CFG[2:0] pins are sampled to determine the
mode the devices will be configured in. Table 12-2 lists the Mode, CFG[0:2] state and the software
CONFIG_MODE parameters. The following subsections break down each configuration mode individually.
Table 12-2. Configuration Modes for the LatticeECP/EC Devices
Configuration Options
Several configuration options are available for each configuration mode. When daisy chaining multiple FPGA
devices, an overflow option is provided for serial and parallel configuration modes. By setting the proper parameter
in the Lattice design software, the selected configuration options are set in the generated bit stream. As the bit
stream is loaded into the device, the selected configuration options will take effect. These options are described in
the following sections and are software selectable by the Lattice design software.
Bypass Option
The Bypass option is used in parallel and serial device daisy chains. When the device has completed configuration
and the Bypass option preference is selected, data coming into the device configuration port will overflow serially
out of DOUT to the DI of the next slave serial device. The Bypass configuration selection is supported in the
CONFIG_MODE selections as shown in Table 12-2.
In serial configuration mode, the Bypass option connects the DI to DOUT, via a bypass register upon completion of
configuration. The bypass register is initialized with a ‘1’ at the beginning of configuration. In parallel configuration
mode, the Bypass option causes the data incoming from D[0:7] to be serially shifted to DOUT after completion of
configuration. The serialized byte wide register will be shifted to DOUT through the bypass register. D0 of the byte
wide data will be shifted out first and followed by D1, D2, and so on.
Once the Bypass option starts, the device will remain in Bypass until the Wake-up sequence completes. One
option to get out of the Bypass option is to toggle CSN and CS1N, which will act as a reset signal. Refer to the
Master Parallel Mode section of this document for more details.
Flow Though Option
The Flow Through option pulls the CSON pin low when the device has completed its configuration. The Flow
Through option can be implemented with either Master or Slave Parallel configuration modes as referenced in
SPI Master
SPIX Master
Master Serial (Bypass OFF)
Master Serial (Bypass ON)
Slave Serial (Bypass OFF)
Slave Serial (Bypass On)
Master Parallel (Flow Through OFF)
Master Parallel (Flow Through ON)
Slave Parallel
Slave Parallel (Bypass ON)
Slave Parallel (Flow Through ON)
ispJTAG (1149.1 interface)
CCJ
allows the device to support different JTAG chain voltages. For further JTAG chain questions, see
Mode
CFG[2]
X
0
0
1
1
1
1
1
1
1
1
1
CFG[1]
12-5
1
1
X
0
0
0
0
0
0
1
1
1
LatticeECP/EC sysCONFIG Usage Guide
CFG[0]
0
1
0
0
1
1
0
0
1
1
1
X
SLAVE_SERIAL
MASTER_PARLLEL
MASTER_PARLLEL_FLOWTHR
SLAVE_PARALLEL
SPI
SPIX
MASTER_SERIAL
MASTER_SERIAL_BYPASS
SLAVE_SERIAL_BYPASS
SLAVE_PARALLEL_BYPASS
SLAVE_PARALLEL_FLOWTHR
Any CONFIG_MODE or NONE1
CONFIG_MODE Parameter