LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 370

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 15-11. MAC9X9MAC Packed into a sysDSP Block
Targeting the sysDSP Block using Simulink
Simulink Overview
Simulink is a graphical add-on (similar to schematic entry) for Matlab, which is produced by Mathworks. For more
information refer to the Simulink web site at www.mathworks.com/products/simulink/.
Why is Simulink Used?
How Does Simulink Fit into the Normal ispLEVER Design Flow?
Once you have converted have your algorithm working in fixed point you can use the Lattice ispDSP Block to create
HDL files, which can be instantiated in your HDL design. Currently there is only support for VHDL.
What Does Lattice Provide?
Lattice provides a library of blocks for the Simulink tool, which include multipliers, adders, registers and other stan-
dard building blocks. Besides the basic building blocks there are a couple of unique Lattice blocks.
Gateways In and Out
Everything between Gateways In and Out represents HDL code. Everything before a Gateway In is the stimulus
your test bench. Everything after a Gateway Out are the signals you will be monitoring in your test bench.
Figure 15-12 is an example.
ispDSP
The ispDSP block is used to convert fixed point Simulink design into HDL files which can be instantiated in your
HDL design. The ispDSP Block is identified by the Lattice logo and can be seen in Figure 21.
• Simulink allows users to create algorithms using floating point numbers
• It helps users convert floating point algorithms into fixed point algorithms
User only allowed
to use lower order
9 bits for each
operand.
MUI18A1[8:0]
MUI18B1[8:0]
MUI18A3[8:0]
MUI18B3[8:0]
SRIB[8:0]
SRIA[8:0]
SROA[8:0]
Notes:
1. These signals are optional.
2. At least one clock is required.
1
1
1
SROB[8:0]
CLK[3:0]
RST[3:0]
18x18 - 3
18x18 - 1
CE[3:0]
1
2
1
1
15-9
+/-
+/-
LatticeECP-DSP sysDSP Usage Guide
ADDNSUB[3,1]
ACCUMSLOAD[3,1]
SIGNEDAB[3,1]
Reg
Reg
Reg
Reg
Out
Out
Out
Out
0
1
2
3
1
1
1
OVERFLOW1
ACCUM1[33:0]
OVERFLOW3
ACCUM3[33:0]
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