LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 417
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 17-8. PAR Options Window
Figure 17-9. Example PAR report (.par) File, Routing Section
The place and route (.par) report file contains execution information about the PAR command run. The report also
shows the steps taken as the program converges on a placement and routing solution. In the routing convergence
example text in Figure 17-9, the number in parenthesis is the timing score after each iteration. In this example, tim-
ing was met after three routing iterations, as can be seen from the (0) timing score.
Using Multiple Placement Iterations (Cost Tables)
Using multiple placement iterations can be achieved by selecting the Advanced Options in Figure 17-8.
As shown in the Advanced Options of Figure 17-8, the number of iterations is set to 10 and the placement start
point is set to iteration 1 (cost table 1). Only the best NCD file is to be saved as per the following line. Once PAR
runs, the tool will loop back through the place and route flow until the number of iterations has reached 10. In this
0 connections routed; 26590 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 11 mins 31 secs
Starting iterative routing.
End of iteration 1
26590 successful; 0 unrouted; (151840) real time: 14 mins 29 secs
Dumping design to file
d:\ip\design.ncd.
End of iteration 2
26590 successful; 0 unrouted; (577) real time: 16 mins 23 secs
Dumping design to file
d:\ip\design.ncd.
End of iteration 3
26590 successful; 0 unrouted; (0) real time: 17 mins 39 secs
Dumping design to file
17-11
Lattice Semiconductor FPGA
Successful Place and Route
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