LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 344

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 12-6. Master and Slave Parallel Daisy Chain
Slave Parallel Mode
In Slave Parallel Mode, a host system sends the configuration data in a byte wide stream to the device. The CCLK,
CSN, CS1N and the WRITEN signal are provided by the host system such as a Master Parallel mode device as
shown in Figure 12-6.
The Slave Parallel configuration mode allows multiple devices to be chained in parallel.
To support asynchronous configuration, where the host may provide data faster than the FPGA can handle it, the
Slave Parallel mode can use the BUSY signal. By driving the BUSY signal high, the Slave Parallel device tells the
host to pause sending data.
Slave Parallel (no overflow option)
Slave Parallel (Bypass ON)
Slave Parallel (Flow Through ON)
RESET/OE
PROM
Mode
D[0:7]
CLK
CS
WRITEN
CCLK
D[0:7]
DONE
INITN
CSN
CS1N
PROGRAMN
CFG[2]
Master Parallel
Lattice FPGA
1
1
1
12-11
CFG[1]
CSON
CFG2
CFG1
CFG0
1
1
1
LatticeECP/EC sysCONFIG Usage Guide
CFG[0]
1
1
1
CCLK
D[0:7]
DONE
INITN
WRITEN
CSN
CS1N
PROGRAMN
SLAVE_PARALLEL
SLAVE_PARALLEL_BYPASS
SLAVE_PARALLEL_FLOWTHR
Lattice FPGA
Slave Parallel
CONFIG_MODE Parameter
CFG2
CFG1
CFG0