MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 107

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Addresses: CMPA_SCR – F1B0h base + 3h offset = F1B3h
Freescale Semiconductor
Reset
Read
Write
HYST_SEL
Bit
Reserved
SMELB
15–8
Field
CFR
7–6
IER
IEF
5
4
3
2
15
0
CMPB_SCR – F1C0h base + 3h offset = F1C3h
CMPC_SCR – F1D0h base + 3h offset = F1D3h
14
0
This read-only bitfield is reserved and always has the value zero.
Hysteresis Select
These control bits are used to select the amount of hysteresis on the analog comparator. Values range
from 0 (least hysteresis) to 3(most hysteresis) with the reset value of 1being equivalent to the hysteresis
found in past comparators in this family.
Stop Mode Edge / Level Interrupt Control
This bit controls whether the CFR and CFF bits are edge sensitive or level sensitive in STOP mode.
0
1
Comparator Interrupt Enable Rising
The IER bit enables the CFR interrupt from the ACM. When this bit is set, an interrupt will be asserted
when the CFR bit is set.
0
1
Comparator Interrupt Enable Falling
The IEF bit enables the CFF interrupt from the ACM. When this bit is set, an interrupt will be asserted
when the CFF bit is set.
0
1
Analog Comparator Flag Rising
During normal operation, the CFR bit is set when a rising edge on COUT has been detected. The CFR bit
is cleared by writing a logic one to the bit. During STOP mode, CFR can be programmed as either edge
or level sensitive via the SMELB bit.
NOTE: Edge detection during STOP is only supported on platforms which allow peripherals to be
0
1
CFR/CFF are Level Sensitive in STOP mode. CFR will be asserted when COUT is high. CFF will be
asserted when COUT is LOW
CFR/CFF are Edge Sensitive in STOP mode. An active low-to-high transition must be seen on COUT
to assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF.
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Rising edge on COMPO has not been detected.
Rising edge on COUT has occurred.
13
0
clocked during STOP modes. If the CFF and CFR flags are to be active during STOP, then
SMELB must be set to “0” for cases where the it is not receiving a clock during STOP.
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
11
0
CMPx_SCR field descriptions
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
HYST_SEL
0
7
1
6
Chapter 3 High Speed Comparator (HSCMP)
0
5
IER
0
4
IEF
0
3
CFR
0
2
CFF
0
1
COU
T
0
0
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