MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 389

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.3
Six registers control and monitor SPI operation. These registers should be accessed only
with word accesses. Accesses other than word lengths result in undefined results. The SPI
bit in the SIM module’s SIM_PCE register must be 1 before the SPI registers can be
changed.
12.3.1 SPI Status and Control Register (QSPI0_SCTRL)
The SCTRL register does the following:
Freescale Semiconductor
offset (hex)
Address
• Select master SPI baud rate
• Determines data shift order
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
0
1
2
3
4
5
Memory Map Registers
QSPI0_SCTRL
QSPI0_DELAY
QSPI0_DXMIT
QSPI0_DRCV
QSPI0_FIFO
Register
DSCTRL
QSPI0_
name
Using BFCLR or BFSET instructions on the SCTRL register
can cause unintended side effects on the status bits.
R
W
R
W
R
W
R
W
R
W
R
W
R15 R14 R13 R12 R11 R10
T15
15
15
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
SPR
T14
14
14
0
0
TFCNT
T13
13
13
0
T12
12
12
SSB_
T11
Preliminary
IN
11
11
0
NOTE
T10
10
10
RFCNT
R9
T9
9
9
Chapter 12 Queued Serial Peripheral Interface (QSPI)
R8
T8
8
8
R7
T7
0
7
7
WAIT
R6
T6
6
6
TFWM
SPE
R5
T5
5
5
R4
T4
0
4
4
R3
T3
3
RFWM
3
R2
T2
2
2
DS
R1
T1
0
1
1
R0
T0
389
0
0