MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 180

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
Timer Status and Control Register (SCTRL)
Comparator Status and Control Register (CSCTRL)
Interrupt Service Routines
To service the CSCTRL[TCF2] interrupts generated by the timer, the interrupt controller
must be configured to enable the interrupts for the particular timer being used.
Additionally the user will need to write an interrupt service routine to do at a minimum
the following:
180
• ONCE=1'b0 (want to count repeatedly)
• LENGTH=1'b1 (want to count until compare value is reached and re-initialize
• DIR=Any (user's choice. The compare register values must be chosen carefully to
• COINIT=1'b0 (user can set this if they need this function)
• OUTMODE=3'b100 (toggle OFLAG output using alternating compare registers)
• OEN = 1'b1 (output enable to allow OFLAG output to be put on an external pin. Set
• OPS = Any (user's choice)
• Make sure the rest of the bits are cleared for this register. We will enable interrupts in
• TCF2EN=1'b1 (allow interrupt to be issued when CSCTRL[TCF2] is set)
• TCF1EN=1'b0 (do not allow interrupt to be issued when CSCTRL[TCF1] is set)
• TCF1=1'b0 (clear timer compare 1 interrupt source flag. This is set when counter
• TCF2=1'b0 (clear timer compare 2 interrupt source flag. This is set when counter
• CL1=2'b10 (load compare register when CSCTRL[TCF2] is asserted)
• CL2=2'b01 (load compare register when CSCTRL[TCF1] is asserted)
• Clear CSCTRL[TCF2] and CSCTRL[TCF1] flags.
• Calculate and write new values for both CMPLD1 and CMPLD2.
counter register)
account for things like roll-under, etc.)
this bit as needed.)
the comparator status and control register instead of in this register.
register equals compare register 1 value and OFLAG is low)
register equals compare register 2 value and OFLAG is high)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor