MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 626

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
All state transitions of the TAP controller occur based on the value of TMS at the time of
a rising edge of TCK. Actions of the instructions occur on the falling edge of TCK in
each controller state illustrated in the TAP controller state diagram. The following table
lists the and descibes the JTAG states.
626
Test Logic Reset (pstate=F)
Run-Test-Idle (pstate-C)
Select Data Register (pstate-7)
Select Instruction Register
(pstate=4)
Capture Data Register (pstate=6)
Shift Data Register (pstate=1)
Exit 1 Data Register (pstate=1)
Pause Data Register (pstate=3)
Exit2 Data Register (pstate=0)
Update Data Register (pstate=5)
State
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
During test-logic-reset, all JTAG test logic is disabled so the device can operate in nor‐
mal mode. This is achieved by initializing the instruction register (IR) with the IDCODE
instruction. By holding TMS high for five rising edges of TCK, the device always remains
in test-logic-reset no matter what state the TAP controller was in previously.
Run-test-idle is a controller state between scan operations. When EOnCE is entered, the
controller remains in run-test-idle mode as long as TMS is held low. When TMS is high
and a rising edge of TCK occurs, the controller moves to the select-DR state.
The select-DR state is a temporary state in which all test data registers selected by the
current instruction retain their previous states. If TMS is held low and a rising edge of
TCK occurs when the controller is in this state, the controller moves into the capture-DR
state and a scan sequence for the selected test date register is initiated. If TMS is held
high and a rising edge of TCK occurs, the controller moves to the select-IR state.
The select-IR state is a temporary state in which all test data registers selected by the
current instruction retain their previous states. If TMS is held low and a rising edge of
TCK occurs when the controller is in this state, the controller moves into the capture-IR
state and a scan sequence for the instruction register is initiated. If TMS is held high and
a rising edge of TCK occurs, the controller moves to the test-logic-reset state.
In this controller state, data can be loaded in parallel into test registers selected by the
current instruction on the rising edge of TCK. If a test data register selected by the cur‐
rent instruction does not have a parallel input, the register retains its previous value.
In this controller state, the test data register is connected between TDI and TDO. This
data is then shifted one stage towards its serial output on each rising edge of TCK. The
TAP controller remains in this state while TMS is held at low. When 1 is applied to TMS
and a positive edge of TCK occurs, the controller moves to the exit1-DR state.
This is a temporary controller state. If TMS is held high, and a rising edge is applied to
TCK while in this state, the controller advances to the update-DR state. This terminates
the scanning process.
This controller state permits shifting of the test data register in the serial path between
TDI and TDO to be temporarily halted. All test data registers selected by the current in‐
struction retain their previous state unchanged. The controller remains in this state while
TMS is held low. When TMS goes high and a rising edge is applied to TCK, the control‐
ler advances to the exit2-DR state.
This is a temporary controller state. If TMS is held high, and a rising edge is applied to
TCK while it is in this state, the scanning process terminates and the TAP controller ad‐
vances to the update-DR state. If TMS is held low and a rising edge of TCK occurs, the
controller advances to the shift-DR state.
All boundary scan registers contain a two-stage data register. It isolates the shifting and
capturing of data on the peripheral from what is applied to internal logic during scan
mode. This register is the second stage, or parallel output, and applies a stimulus to in‐
ternal logic. Data is latched on the parallel output of these test data registers from the
shift register path on the falling edge of TCK in the update-DR state. On a rising edge of
TCK, the controller advances to the select_dr state if TMS is held high or the run-test-
idle state if TMS is held low.
Table continues on the next page...
Table 21-3. JTAG States
Preliminary
Description
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