MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 173

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

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6.6.2.9 Triggered-Count Mode 2
If CSCTRL[TCI] is set and CTRL[CM] is set to '110', the counter will begin counting the
primary clock source after a positive transition (negative edge if SCTRL[IPS]=1) of the
secondary input occurs. The counting will continue until a compare event occurs or
another positive input transition is detected. If a second input transition occurs before a
terminal count was reached, the counter will reload and continue counting. When
CSCTRL[TCI] is set, the OFLAG output mode, CTRL[OUTMODE], should probably be
set to '101' (cleared on init, set on compare) to ensure the output will be in a known state
after the second input transition and subsequent reload takes place.
Example: 6.6.2.9.1 Triggered Count Mode 2Example
Freescale Semiconductor
//
//
//
//
//
//
void Pulse_Init(void)
{
}
/* TMRA1_CTRL: CM=0,PCS=3,SCS=2,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */
setReg(TMRA1_CTRL,0x0700);
/* TMRA1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=1,IEF=0,IEFIE=0,IPS=0,INPUT=0,
setReg(TMRA1_SCTRL,0x1000);
setReg(TMRA1_CNTR,0x00);
setReg(TMRA1_LOAD,0x00);
setReg(TMRA1_COMP1,0x0012);
/* TMRA1_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,
setReg(TMRA1_CSCTRL,0x00);
setRegBitGroup(TMRA1_CTRL,CM,0x06);
Secondary
This example uses TMRA1 for triggered mode counting.
Timer input 3 is used as the primary count source.
Timer input 2 is used for the trigger input.
Count
(See Processor Expert PulseAccumulator bean.)
0
0
Figure 6-121. Triggered Count Mode 2 (CTRL[LENGTH]=0)
Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
0
TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
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5
/* Set up mode */
/* Reset counter register */
/* Reset load register */
/* Set up compare 1 register */
/* Run counter */
6
Preliminary
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3
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1
Chapter 6 Quad Timer (TMR)
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