MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 162

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
162
ALT_LOAD
Reserved
DBG_EN
FAULT
15–14
ROC
Field
TCI
UP
13
12
11
10
9
8
Debug Actions Enable
These bits allow the TMR module to perform certain actions in response to the chip entering debug mode.
00
01
10
11
Fault Enable
The selected secondary input acts as a fault signal so that the timer OFLAG is cleared when the
secondary input is set. When the secondary input is used in this mode, there is no resynchronization of
the input so that there is a combinational path to clear the OFLAG. Fault inputs less than two clock
periods wide will not be latched. Latched faults will be cleared the next time that the counter logic sets the
OFLAG.
0
1
Alternative Load Enable
This bit allows for an alternative method for loading the counter during modulo counting. Normally, the
counter can be loaded only with the value from the LOAD register. When this bit is set, the counter is
loaded from the LOAD register when counting up and a match with COMP1 occurs, or the counter is
loaded from the CMPLD2 register when counting down and a match with COMP2 occurs.
0
1
Reload on Capture
This bit enables the capture function to cause the counter to be reloaded from the LOAD register.
0
1
Triggered Count Initialization Control
This bit is used during triggered count mode, CTRL[CM] = 110, to enable the counter to be re-initialized
when a second trigger occurs while the counter is still counting. Normally, the second trigger causes the
counting to stop/pause until a third trigger occurs. With this bit set, a second trigger event causes the
counter to re-initialize and continue counting.
0
1
Counting Direction Indicator
This read-only bit is used during quadrature count mode, CTRL[CM] = 100, to read the direction of the
last count. CTRL[DIR] reverses the sense of this bit.
0
1
This read-only bit is reserved and always has the value zero.
Fault function disabled.
Fault function enabled.
Counter can be re-initialized only with the LOAD register.
Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
Do not reload the counter on a capture event.
Reload the counter on a capture event.
Stop counter upon receiving a second trigger event while still counting from the first trigger event.
Reload the counter upon receiving a second trigger event while still counting from the first trigger
event.
The last count was in the DOWN direction.
The last count was in the UP direction.
Continue with normal operation during debug mode. (default)
Halt TMR counter during debug mode.
Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
Both halt counter and force output to 0 during debug mode.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
TMRx_CSCTRL field descriptions
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Preliminary
Description
Freescale Semiconductor