MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 227

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
RELOAD_SEL
FORCE_SEL
CLK_SEL
FORCE
FRCEN
Field
5–3
1–0
7
6
2
Force Initialization Enable
This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by
CTRL2[INIT_SEL]. This is a software controlled initialization.
0
1
Force Initialization
If CTRL2[FORCE_SEL] is set to 000, writing a 1 to this bit results in a FORCE_OUT event. This causes
the following actions to be taken:
This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
000
001
010
011
100
101
110
111
Reload Source Select
This read/write bit determines the source of the RELOAD signal for this submodule. When this bit is set,
MCTRL[LDOK[0]] for submodule 0 should be used since the local MCTRL[LDOK] will be ignored.
0
1
Clock Source Select
These read/write bits determine the source of the clock signal for this submodule.
00
01
10
11
• The PWMA and PWMB output pins will assume values based on DTSRCSEL[SMxSEL23] and
• If CTRL2[FRCEN] is set, the counter value will be initialized with the INIT register value.
Initialization from a FORCE_OUT event is disabled.
Initialization from a FORCE_OUT event is enabled.
The local RELOAD signal is used to reload registers.
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be
used in submodule 0 as it will force the RELOAD signal to logic 0.
The IPBus clock is used as the clock for the local prescaler and counter.
EXT_CLK is used as the clock for the local prescaler and counter.
Submodule 0’s clock (AUX_CLK) is used as the source clock for the local prescaler and counter.
This setting should not be used in submodule 0 as it will force the clock to logic 0.
reserved
DTSRCSEL[SMxSEL45].
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
The master force signal from submodule 0 is used to force updates. This setting should not be
used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
The local reload signal from this submodule is used to force updates.
The master reload signal from submodule0 is used to force updates. This setting should not be
used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
The local sync signal from this submodule is used to force updates.
The master sync signal from submodule0 is used to force updates. This setting should not be used
in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
reserved
PWM_SM3CTRL2 field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
Description
227