MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 464

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
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13.4.2.3 Receive Structures
The received messages are stored in a five stage input FIFO. The five message buffers are
alternately mapped into a single memory area. The background receive buffer (RxBG) is
exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is
addressable by the CPU. This scheme simplifies the handler software because only one
address area is applicable for the receive process.
All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier
(standard or extended), the data contents, and a time stamp, if enabled.
The receiver full flag (RXF) signals the status of the foreground receive buffer. When the
buffer contains a correctly received message with a matching identifier, this flag is set.
On reception, each message is checked to see whether it passes the filter and
simultaneously is written into the active RxBG. After successful reception of a valid
message, the MSCAN shifts the content of RxBG into the receiver FIFO
flag, and generates a receive interrupt to the CPU
the received message from the RxFG and then reset the RXF flag to acknowledge the
interrupt and to release the foreground buffer. A new message, which can follow
immediately after the IFS field of the CAN frame, is received into the next available
RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier,
transmission errors, etc.) the actual contents of the buffer will be over-written by the next
message. The buffer will then not be shifted into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own transmitted
messages into the background receive buffer, RxBG, but does not shift it into the receiver
FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus.
The exception to this rule is in loopback mode where the MSCAN treats its own
messages exactly like all other incoming messages. The MSCAN receives its own
transmitted messages in the event that it loses arbitration. If arbitration is lost, the
MSCAN must be prepared to become a receiver.
An overrun condition occurs when all receive message buffers in the FIFO are filled with
correctly received messages with accepted identifiers and another message is correctly
received from the CAN bus with an accepted identifier. The latter message is discarded
and an error interrupt with overrun indication is generated if enabled. The MSCAN
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4. Only if the RXF flag is not set.
5. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
,
5
. The user's receive handler must read
Freescale Semiconductor
4
, sets the RXF