MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 237

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.37 PWM SM3 Output Trigger Control Register (PWM_SM3TCTRL)
Address: PWM_SM3TCTRL – F300h base + A5h offset = F3A5h
Freescale Semiconductor
Reset
Read
Write
OUT_TRIG_EN
Bit
Reserved
CMPIE
CX1IE
CX0IE
15–6
Field
Field
5–0
5–0
7
6
15
0
14
0
0
1
Capture X 1 Interrupt Enable
This bit allows the STS[CFX1] flag to create an interrupt request to the CPU.
0
1
Capture X 0 Interrupt Enable
This bit allows the STS[CFX0] flag to create an interrupt request to the CPU.
0
1
Compare Interrupt Enables
These bits enable the STS[CMPF] flags to cause a compare interrupt request to the CPU.
0
1
This read-only bitfield is reserved and always has the value zero.
Output Trigger Enables
These bits enable the generation of OUT_TRIG0 and OUT_TRIG1 outputs based on the counter value
matching the value in one or more of the VAL0-5 registers. VAL0, VAL2, and VAL4 are used to generate
OUT_TRIG0 and VAL1, VAL3, and VAL5 are used to generate OUT_TRIG1. The OUT_TRIGx signals are
only asserted as long as the counter value matches the VALx value, therefore up to six triggers can be
generated (three each on OUT_TRIG0 and OUT_TRIG1) per PWM cycle per submodule.
0
1
Interrupt request disabled for STS[CFB0].
Interrupt request enabled for STS[CFB0].
Interrupt request disabled for STS[CFX1].
Interrupt request enabled for STS[CFX1].
Interrupt request disabled for STS[CFX0].
Interrupt request enabled for STS[CFX0].
The corresponding STS[CMPF] bit will not cause an interrupt request.
The corresponding STS[CMPF] bit will cause an interrupt request.
OUT_TRIGx will not set when the counter value matches the VALx value.
OUT_TRIGx will set when the counter value matches the VALx value.
13
0
PWM_SM3INTEN field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_SM3TCTRL field descriptions
11
0
0
10
0
0
9
Preliminary
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
0
8
Description
Description
0
7
0
6
0
5
0
4
OUT_TRIG_EN
0
3
0
2
0
1
0
0
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