MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 362

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
11.3.5 QSCI Data Register (QSCIx_DATA)
Read: anytime. Reading accesses the SCI receive data register.
Write: anytime. Writing accesses the SCI transmit data register.
Addresses: QSCI0_DATA – F1E0h base + 4h offset = F1E4h
362
Reset
Read
Write
TRANSMIT_
RECEIVE_
Bit
Reserved
Reserved
DATA
15–9
Field
RAF
Field
2–1
8–0
0
15
0
QSCI1_DATA – F1F0h base + 4h offset = F1F4h
14
0
This read-only bitfield is reserved and always has the value zero.
Receiver Active Flag
This bit is set when the receiver detects a 0 during the RT1 time period of the start bit search. RAF is
cleared when the receiver detects false start bits (usually from noise or baud rate mismatch) or when the
receiver detects a preamble.
0
1
This read-only bitfield is reserved and always has the value zero.
RECEIVE_DATA: Received data (when reading this register)
TRANSMIT_DATA: Data to be transmitted (when writing this register)
If STAT[TDRE] is set, writes to the transmit data field are ignored unless STAT has been read with
STAT[TDRE] set. However, when CTRL2[FIFO_EN] or CTRL2[TDE] are set, you can write to the SCI
data register without first reading STAT with STAT[TDRE] set.
If STAT[RDRF] is set, reads from the receive data field are ignored unless STAT has been read with
STAT[RDRF] set. However, when CTRL2[FIFO_EN] or CTRL2[RDE] are set, you can read from the SCI
data register without first reading STAT with STAT[RDRF] set.
NOTE: When the data format is configured for 8-bit data, bits 7 to 0 contain the data.
No reception in progress
Reception in progress
13
0
QSCIx_STAT field descriptions (continued)
12
0
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
QSCIx_DATA field descriptions
10
0
0
9
Preliminary
0
8
Description
Description
0
7
0
6
RECEIVE_TRANSMIT_DATA
0
5
0
4
0
3
Freescale Semiconductor
0
2
0
1
0
0