MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 342

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
Any master detecting either scenario can assume the bus is free when SHTF1 rises. A
HIGH timeout occurs in scenario 2 if a master ever detects that both the BUSY bit is high
and SHTF1 is high.
When the SMBDAT signal is low and the SMBCLK signal is high for a period of time,
the other kind of timeout occurs. The time period must be defined in software. SHTF2 is
used as the flag when the time limit is reached. This flag is also an interrupt resource, so
it also triggers IICIF.
10.4.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
The following figure illustrates the definition of the timeout intervals T
T
clock cycles for a period greater than T
defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK
TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF.
A master is allowed to abort the transaction in progress to any slave that violates the
T
STOP condition at the conclusion of the byte transfer in progress. When a slave, the I2C
module must not cumulatively extend its clock cycles for a period greater than
T
TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF.
342
LOW:MEXT
LOW:SEXT
LOW:SEXT
. When in master mode, the I2C module must not cumulatively extend its
or T
during any message from the initial START to the STOP. When CSMBCLK
CSMBCLK TIMEOUT SEXT and CSMBCLK TIMEOUT
MEXT are optional functions that are implemented in the
second step.
SDA
SCL
TIMEOUT,MIN
Start
Figure 10-37. Timeout measurement intervals
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
T
LOW:MEXT
specifications. To abort the transaction, the master issues a
ClkAck
LOW:MEXT
Preliminary
NOTE
T
T
LOW:SEXT
LOW:MEXT
within a byte, where each byte is
ClkAck
T
LOW:MEXT
LOW:SEXT
Stop
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and