MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 334

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
10.4.1 I2C Protocol
The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data
transfers. All devices connected to it must have open drain or open collector outputs. A
logic AND function is exercised on both lines with external pull-up resistors. The value
of these resistors depends on the system.
Normally, a standard instance of communication is composed of four parts:
The STOP signal should not be confused with the CPU STOP instruction. The following
figure illustrates I2C bus system communication.
334
1. START signal
2. Slave address transmission
3. Data transfer
4. STOP signal
Start Signal
S D A
S C L
S D A
SCL
Signal
Start
M S B
M S B
A D 7
A D 7
1
1
A D 6 A D 5
A D 6
2
2
C a llin g A d d re s s
C a llin g A d d re s s
A D 5
3
3
A D 4
A D 4
Figure 10-35. I2C Bus Transmission Signals
4
4
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
A D 3 A D 2 A D 1
A D 3 A D 2 A D 1
5
5
6
6
7
7
R e a d /
W rite
R e a d /
W rite
R /W
R /W
L S B
L S B
8
8
Ack
Ack
Bit
Bit
9
Preliminary
9
X X
Repeated
X X X
Signal
Start
M S B
M S B
A D 7
D 7
1
1
A D 6
D 6
2
2
N e w C a llin g A d d re s s
D 5
A D 5
3
3
D a ta B y te
A D 4
D 4
4
4
A D 3 A D 2 A D 1
D 3
5
5
D 2
6
6
D 1
7
7
Freescale Semiconductor
R e a d /
W rite
L S B
L S B
R /W
D 0
8
8
Ack
No
Bit
Ack
No
Bit
9
9
Signal
Signal
Stop
Stop