MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 392

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map Registers
12.3.2 SPI Data Size and Control Register (QSPI0_DSCTRL)
This read/write register determines the data length for each transaction. The master and
slave must transfer the same size data on each transaction. A new value will only take
effect at the time the SPI is enabled (SPE bit in SCTRL register set from a zero to a one).
In order to have a new value take effect, disable then re-enable the SPI with the new
value in the register.
To utilize the SS_B control functions in master mode the appropriate bit must be set in
GPIO_x_PER register to enable peripheral control of the SS_B pin.
Address: QSPI0_DSCTRL – F200h base + 1h offset = F201h
392
Reset
Read
Write
Bit
MODF
OVRF
SPTE
Field
WOM
2
1
0
15
0
14
0
0
Overflow
0
1
Mode Fault
This clearable, read-only flag is set in a slave SPI if the SS_B pin goes high during a transaction with the
MODFEN bit set. In a master SPI, the MODF flag is set if the SS_B pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by writing a one to the MODF bit when it is set.
0
1
SPI Transmitter Empty
This clearable, read-only flag is set each time the transmit data register transfers data into the shift
register and there is no more new data available in the Tx queue (Tx FIFO is empty). SPTE generates an
interrupt request if the SPTIE bit in the SPI control register is set. SPTE is cleared by writing to the
QSPI0_DXMIT register.
NOTE: Do not write to the SPI data register unless the SPTE bit is high or data may be lost.
0
1
No overflow
Overflow
SS_B pin at appropriate logic level
SS_B pin at inappropriate logic level
Transmit data register or FIFO is not empty. (If using the FIFO, then read the TFCNT field to
determine how many words can be written safely.)
Transmit data register or FIFO is empty.
13
0
0
QSPI0_SCTRL field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
SSB_
IN
11
0
10
1
SSB_
ODM
0
9
Preliminary
0
8
Description
SSB_
DDR
0
7
STRB
SSB_
0
6
0
5
SPR3
0
4
1
3
Freescale Semiconductor
1
2
DS
1
1
1
0