MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 627

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.5 Clocks
TCK is the sole clock used by the master TAP module. If the EOnCE module is not being
accessed using the master or DSC core TAP controllers, the maximum TCK frequency is
one-quarter the maximum frequency for the DSC core. When the EOnCE module is
accessed through the DSC core TAP controller, the maximum frequency for TCK is one
eighth the maximum frequency for the DSC core.
Freescale Semiconductor
Capture Instruction Register
(pstate = E)
Shift Instruction Register (pstate =
A)
Exit1 Instruction Register (pstate
= 9)
Pause Instruction Register (pstate
= B)
Exit2 Instruction Register (pstate
= 8)
Update Instruction Register
(pstate = D)
TCK
Clock
State
1
Priority
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
When the TAP controller is in this state and a rising edge of TCK occurs, the controller
advances to the exit1-IR state if TMS is held at one, or the shift-IR state if TMS is held at
zero.
In this controller state, the shift register contained in the instruction register is connected
between TDI and TDO and shifts data one stage toward its serial output on each rising
edge of TCK. When the TAP controller is in this state and a rising edge of TCK occurs,
the controller advances to the exit1-IR state if TMS is held at one or remains in the shift-
IR state if TMS is held at zero.
This is a temporary controller state. If TMS is held high, and a rising edge is applied to
TCK while in this state, the controller advances to the update-IR state. This terminates
the scanning process. If TMS is held low and a rising edge of TCK occurs the controller
advances to the pause-IR state.
This controller state allows shifting of the instruction register in the serial path between
TDI and TDO to be temporarily halted. All test data registers selected by the current in‐
struction retain their previous state unchanged. The controller remains in this state while
TMS is held low. When TMS goes high and a rising edge is applied to TCK, the control‐
ler advances to the exit2-IR state.
This is a temporary controller state. If TMS is held high, and a rising edge is applied to
TCK while in this state, the scanning process terminates and the TAP controller advan‐
ces to the update-IR state. If TMS is held low and a rising edge of TCK occurs, the con‐
troller advances to the shift-IR state.
During this state, the instruction shifted into the instruction register is latched from the
shift register path on the falling edge of TCK and into the instruction latch. It becomes
the current instruction. On a rising edge of TCK, the controller advances to the selector
state if TMS is held high, or the run-test-idle state if TMS is held low.
Table 21-3. JTAG States (continued)
Table 21-4. JTAG Clock Summary
External
Source
Preliminary
This user-provided clock shifts data and controls the state
machine.
Chapter 21 Joint Test Action Group (JTAG) Port
Description
Characteristics
627