MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 183

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 6 Quad Timer (TMR)
Use caution when changing COMP1 and COMP2 while the counter is active. If the
counter has already passed the new value, it will count to FFFFh or 0000h, roll over, then
begin counting toward the new value. The check is: Count=CMPx, not Count > COMP1
or Count < COMP2.
The use of the CMPLD1 and CMPLD2 registers to compare values will help to minimize
this problem.
>
6.6.2.16 Usage of Compare Load Registers
The CMPLD1, CMPLD2, and CSCTRL registers offer a high degree of flexibility for
loading compare registers with user-defined values on different compare events. To
ensure correct functionality while using these registers we strongly suggest using the
following method described in this section.
The purpose of the compare load feature is to allow quicker updating of the compare
registers. In the past, a compare register could be updated using interrupts. However,
because of the latency between an interrupt event occurring and the service of that
interrupt, there was the possibility that the counter may have already counted past the
new compare value by the time the compare register was updated by the interrupt service
routine. The counter would then continue counting until it rolled over and reached the
new compare value.
To address this, the compare registers are now updated in hardware in the same way the
counter register is re-initialized to the value stored in the load register. The compare load
feature allows the user to calculate new compare values and store them in to the
comparator load registers. When a compare event occurs, the new compare values in the
comparator load registers are written to the compare registers eliminating the use of
software to do this.
The compare load feature is intended to be used in variable frequency PWM mode. The
COMP1 register determines the pulse width for the logic low part of OFLAG and
COMP2 determines the pulse width for the logic high part of OFLAG. The period of the
waveform is determined by the COMP1 and COMP2 values and the frequency of the
primary clock source. See the following figure.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor
183