MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 335

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.4.1.1 START Signal
The bus is free when no master device is engaging the bus (both SCL and SDA are high).
When the bus is free, a master may initiate communication by sending a START signal.
A START signal is defined as a high-to-low transition of SDA while SCL is high. This
signal denotes the beginning of a new data transfer (each data transfer might contain
several bytes of data) and brings all slaves out of their idle states.
10.4.1.2 Slave Address Transmission
Immediately after the START signal, the first byte of a data transfer is the slave address
transmitted by the master. This address is a 7-bit calling address followed by an R/W bit.
The R/W bit tells the slave the desired direction of data transfer.
Only the slave with a calling address that matches the one transmitted by the master
responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling
SDA low at the ninth clock.
No two slaves in the system may have the same address. If the I2C module is the master,
it must not transmit an address that is equal to its own slave address. The I2C module
cannot be master and slave at the same time. However, if arbitration is lost during an
address cycle, the I2C module reverts to slave mode and operates correctly even if it is
being addressed by another master.
10.4.1.3 Data Transfers
When successful slave addressing is achieved, data transfer can proceed on a byte-by-
byte basis in the direction specified by the R/W bit sent by the calling master.
All transfers that follow an address cycle are referred to as data transfers, even if they
carry subaddress information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low. Data must be
held stable while SCL is high. There is one clock pulse on SCL for each data bit, and the
MSB is transferred first. Each data byte is followed by a ninth (acknowledge) bit, which
is signaled from the receiving device by pulling SDA low at the ninth clock. In summary,
one complete data transfer needs nine clock pulses.
Freescale Semiconductor
• 1 = Read transfer: The slave transmits data to the master
• 0 = Write transfer: The master transmits data to the slave
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Chapter 10 Inter-Integrated Circuit (I2C)
335