MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 129

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.2.1 Control Register (DAC_CTRL)
Address: DAC_CTRL – F1A0h base + 0h offset = F1A0h
Freescale Semiconductor
offset (hex)
Reset
Read
Write
Address
FILT_CNT
Bit
FILT_EN
2
2
3
3
4
4
15–13
Field
12
15
1
DAC_MAXVAL
DAC_MAXVAL
DAC_MINVAL
DAC_MINVAL
FILT_CNT
[FORMAT=0]
[FORMAT=1]
[FORMAT=0]
[FORMAT=1]
[FORMAT=0]
[FORMAT=1]
DAC_STEP
DAC_STEP
Register
name
14
1
Glitch Filter Count Bits
On chips whose maximum IPBus clock frequency is 32MHz or less, this field represents the number of
IPBus clock cycles that the DAC output is held unchanged after new data is presented to the analog
DAC’s inputs. On chips that have IPBus clock frequencies higher than 32MHz, then the number of IPBus
clock cycles that are delayed is 2*CTRL[FILT_CNT]+1. Approximately 240nsec is needed for worst case
settling of the DAC output, therefore, a value of 7 should be used for both 32MHZ operation (7 IPBus
clock cycles of delay) and for 60MHz operation (15 IPBus clock cycles of delay).
NOTE: When using the glitch filter be sure that the filter count is less than the update count otherwise
Glitch Filter Enable
This bit enables the glitch suppression filter. This introduces a latency based on CTRL[FILT_CNT] for
DAC updates.
13
1
R
W
R
W
R
W
R
W
R
W
R
W
the DAC output will never be updated.
12
1
15
15
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
14
14
11
0
DAC_CTRL field descriptions
0
0
0
13
13
Table continues on the next page...
10
0
12
12
0
9
Preliminary
11
11
0
MAXVAL
0
MINVAL
8
10
10
STEP
Description
9
9
0
7
Chapter 5 12-Bit Digital-to-Analog Converter (DAC)
8
8
0
6
7
7
UP
0
5
MAXVAL
MINVAL
6
6
STEP
0
4
5
5
4
4
0
3
3
3
0
2
2
2
0
0
0
0
1
1
1
1
0
129
0
0